Open Access Journal

ISSN : 2394-6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

ISSN : 2394-6849 (Online)

Design of 4x4 Reversible Multiplier using Reversible TSG Gate

Author : Veena Durgam 1 Dr. K. Ragini 2 Divya Durgam 3

Date of Publication :25th March 2021

Abstract: Multipliers are very important components of any processor or computing machine. The performance of microcontrollers and Digital signal processors are evaluated based on the number of multiplications performed in a unit of time. Hence better multiplier architectures are assured to increase the efficiency of the system. The reversible multiplier is one such promising solution. In this paper, a 4x4 reversible unsigned multiplier is being designed. The Fredkin gates (FRG) are used for producing the partial products and Thapliyal Srinivas Gate (TSG) singly can be used as a half adder and as a full adder for the addition of partial products. The design is implemented using Xilinx ISE 14.7 design suite.

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DOI : 10.36647/ijerece/0000