Author : Veena Durgam 1
Date of Publication :25th March 2021
Abstract: Multipliers are very important components of any processor or computing machine. The performance of microcontrollers and Digital signal processors are evaluated based on the number of multiplications performed in a unit of time. Hence better multiplier architectures are assured to increase the efficiency of the system. The reversible multiplier is one such promising solution. In this paper, a 4x4 reversible unsigned multiplier is being designed. The Fredkin gates (FRG) are used for producing the partial products and Thapliyal Srinivas Gate (TSG) singly can be used as a half adder and as a full adder for the addition of partial products. The design is implemented using Xilinx ISE 14.7 design suite.
- H. Thapliyal, and M. Srinivas, "Novel reversible multiplier architecture using reversible TSG gate."
- M. Haghparast, S. J. Jassbi, K. Navi, et al., “Design of a novel reversible multiplier circuit using HNG gate in nanotechnology,” World Appl. Sci. J, vol. 3, no. 6, pp. 974- 978, 2008
- M. Haghparast, M. Mohammadi, K. Navi, et al., “Optimized reversible multiplier circuit,” Journal of Circuits, Systems, and Computers, vol. 18, no. 02, pp. 311-323, 2009.
- R. Landauer, "Irreversibility and heat generation in the computing process," IBM journal of research and development, vol. 5, no. 3, pp. 183-191, 1961.
- C. H. Bennett, "Logical reversibility of computation," IBM journal of research and development, vol. 17, no. 6, pp. 525-532, 1973.
- M. Perkowski, L. Jozwiak, P. Kerntopf, et al., "A general decomposition for reversible logic." pp. 119- 138.
- M. Perkowski, and P. Kerntopf, "Reversible Logic. Invited tutorial."
- H. Thapliyal, and M. Srinivas, "A novel reversible TSG gate and its application for designing reversible carry look-ahead and other adder architectures." pp. 805-817
- M. Shams, M. Haghparast, and K. Navi, “Novel reversible multiplier circuit in nanotechnology,” World Appl. Sci. J, vol. 3, no. 5, pp. 806-810, 2008
- P. Kerntopf, M. A. Perkowski, and M. H. Khan, "On the universality of general reversible multiple-valued logic gates." pp. 68-73.
- M. Ehsanpour, P. Moallem, and A. Vafaei, "Design of a novel reversible multiplier circuit using modified full adder." pp. V3-230-V3-234.
- W. C. Athas, and L. Svensson, "Reversible logic issues in adiabatic CMOS." pp. 111- 118.
- T. Toffoli, “Reversible Computing” Tech memoMIT/LCS/TM-151, MIT Lab for Computer Science 1980.
- Fredkin E. Fredkin and T. Toffoli, “Conservative Logic”, Int’I J. Theoretical Physics Vol 21, pp.219- 253, 1982.
- Peres, “Reversible Logic and Quantum Computers”, Physical Review A, 32:3266-3276, 1985.
- M. S. Islam, M. Rahman, Z. Begum, et al., “Lowcost quantum realization of reversible multiplier circuit,” Information technology journal, vol. 8, no. 2, pp. 208-213, 2009