Author : Ummadisetti Gowthami 1
Date of Publication :17th May 2021
Abstract: In this paper, we present the simulation of silicon nanowire field effect transistor (SNW FETs) with multiple gates. The simulation of SNW FETs with multiple gates such as top-gate, double-gate, tri-gate, pi-gate, omega-gate and Gate-all-around gate structures are performed based on Current-Voltage (I-V) characteristics using Nanohub Multi-gate Nanowire FET simulator. Simulation studies are performed based on Current Voltage characteristics of Multi gate Nanowire FET. Effects of varying oxide thickness in multiple gates are also presented.
Reference :
-
- R. H. Dennard, F. H. Gaensslen, H. Yu, V. L. Rideout, E. Bassous and A. R. LeBlanc, "Design of ion-implanted MOSFET's with very small physical dimensions," in IEEE Journal of SolidState Circuits, vol. 9, no. 5, pp. 256-268, Oct. 1974,
- Moore G.E. IEDM Technical Digest. 1975;11- 13.
- A. M. Ionescu. Electronic devices: Nanowire transistors made easy. Nature Nanotechnology, 5(3):178-179, 2010.
- M. Shin, "Efficient simulation of silicon nanowire field effect transistors and their scaling behavior," J. Appl. Phys. 101, 024510 (2007)
- BS Doyle, S Datta, M Doczy, S Hareland, B Jin, J Kavalieros, T Linton, A Murthy, R Rios, R Chau (Apr. 2003), “High performance fully depleted tri-gate COMS transistors”, IEEE Trans. Electron Device Lett.,Volume 24, Issue 4, pp. 263–265
- Vimala P, Balamurugan N. B., (2015) "Comparative Analysis of Quantum Effects in Nano-Scale Multigate MOSFETs Using Variational Approach”, J of Eng. Sci. & Tec., Volume 10, Issue 2, pp. 224–234.
- H. Lou, M. Chan (Jul. 2011), Silicon-Based Nanowire MOSFETs: From Process and Device physics to Simulation and Modeling
- Hao Zhu (July 5th 2017). Semiconductor Nanowire MOSFETs and Applications, Nanowires - New Insights, Khan Maaz, IntechOpen, DOI: 10.5772/67446.
- Iwai, H., Natori, K., Shiraishi, K. et al. Si nanowire FET and its modeling. Sci. China Inf. Sci. 54, 1004–1011 (2011). https://doi.org/10.1007/s11432-011-4220-0
- T. Grap, F. Riederer, C. Gupta and J. Knoch, "Buried multi-gate InAs-nanowire FETs," 2017 47th European Solid-State Device Research Conference (ESSDERC), Leuven, Belgium, 2017, pp. 82-85, doi: 10.1109/ESSDERC.2017.8066597.