Author : Sikharam Giridhar Sai 1
Date of Publication :17th May 2021
Abstract: DCT (Discrete Cosine Transform) communicates finite succession of information regarding the amount of cosine functions oscillating at various frequencies. The utilization of cosine is basic for compression as incidentally, less cosine capacities are expected to estimate through for differential conditions. Being a transformation technique and one among the complex ones, any n point DCT has complex calculation procedures that also uses matrices. This results in a larger area and power trade-offs. This paper tries to cope up with these particular trade-offs and try to find more efficient ways by using the floating point multiplication/multiplier techniques as the floating point numbers are utilized to address non integer fractional numbers are utilized in most designing and specialized computations. The proposed DCT module operates with very high frequency and with very low dynamic power dissipation.
Reference :
-
- Ahmed, Nasir, T_ Natarajan, and Kamisetty R. Rao. "Discrete cosine transform." IEEE transactions on Computers 100.1 (1974): 90-93.
- Strang, Gilbert. "The discrete cosine transform." SIAM review 41.1 (1999): 135-147.
- Zhou, Jianqin, and Ping Chen. "Generalized discrete cosine transform." 2009 Pacific-Asia Conference on Circuits, Communications and Systems. IEEE, 2009.
- Wang, Zhongde, and B. Hunt. "The discrete cosine transform--A new version." In ICASSP'83. IEEE International Conference on Acoustics, Speech, and Signal Processing, vol. 8, pp. 1256-1259. IEEE, 1983.
- Cho, Nam Ik, and San Uk Lee. "Fast algorithm and implementation of 2-D discrete cosine transform." IEEE transactions on circuits and systems 38.3 (1991): 297-305.
- Vetterli, Martin. "Fast 2-D discrete cosine transform." ICASSP'85. IEEE International Conference on Acoustics, Speech, and Signal Processing. Vol. 10. IEEE, 1985.
- Al-Ashrafy, Mohamed, Ashraf Salem, and WagdyAnis. "An efficient implementation of floating point multiplier." 2011 Saudi International Electronics, Communications and Photonics Conference (SIECPC). IEEE, 2011.
- Hickmann, Brian, Andrew Krioukov, Michael Schulte, and Mark Erle. "A parallel IEEE P754 decimal floating-point multiplier." In 2007 25th International Conference on Computer Design, pp. 296-303. IEEE, 2007.
- Kanhe, Aniruddha, Shishir Kumar Das, and Ankit Kumar Singh. "Design and implementation of floating point multiplier based on vedic multiplication technique." 2012 international conference on communication, information & computing technology (ICCICT). IEEE, 2012.
- Zhang, Hang, Wei Zhang, and John Lach. "A lowpower accuracy- configurable floating point multiplier." 2014 IEEE 32nd International Conference on Computer Design (ICCD). IEEE, 2014
- Even, Guy, Silvia M. Mueller, and Peter-Michael Seidel. "A dual precision IEEE floating-point multiplier." Integration 29.2 (2000): 167-180