Author : Sowjanya.K 1
Date of Publication :31st July 2021
Abstract: There are different optimization criteria in the design and development of speech compression algorithms in that Codec2 vocoder algorithm is one of an efficient sinusoidal coding with very high compression rate down to 450 bit/s. In this paper, to increase the performance of voice decoding process, efficient hardware architecture of Codec2 low bit-rate speech decoder is designed. The decoding processes of codec2 is based on sinusoidal model .Although the sinusoidal decoding algorithm is complicated with many arithmetic operations such as the arithmetic of complex numbers, FFT, FIR filter, division, trigonometry, exponential and logarithm functions, several techniques were explored to optimize and parallelize a data path of the proposed hardware. The proposed hardware implementation is done using verilog (hardware description language) and synthesized on Xilinx Artix-7 FPGA.
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- An Efficient Hardware Architecture of Codec2 Low Bit-rate Speech Decoder | IEEE Conference Publication | IEEE Xplore