Open Access Journal

ISSN : 2394 - 6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering
Call For Paper : Vol 11, Issue 03, March 2024

ISSN : 2394-6849 (Online)

Call for Paper

Vol 11, Issue 03, March 2024

Indexing

Study of Dynamic Comparators on the basis of Energy Consumption

Author : Abhyuday Singh 1 Dr. Manisha Bharti 2

PDF

Date of Publication :31st December 2021

Abstract: This paper is aimed towards the comparison between different dynamic comparators on some parameters like noise produced, uses of area, power consumption and use of any external circuitry. In this paper mainly double tail latch comparator, cross coupled double tail latch comparator, strong arm latch (SA) and dynamic bias comparator is compared in which at the same input rms noise level and at similar area usages, the power consumption of cross coupled double tail latch comparator is reduced nearly one fourth because the energy consumption per comparison is also reduced.

Reference :

    1. Subhash Chevella, Daniel O’Hare and Ivan O’Connell, “A Low Power 1V Supply Dynamic Comparator”, IEEE Solid-State Circuits Letters (Volume: 3), 15 July 2020, DOI: v10.1109/LSSC.2020.3009437
    2.  B. Razavi,” The StrongARM Latch [A Circuit for All Seasons]”, in IEEE SSC Magazine, vol. 7, no. 2, pp. 12-17, Spring 2015.
    3. H. S. Bindra, C. E. Lokin, A.-J. Annema, and B. Nauta, “A 30fJ/comparison dynamic bias comparator,” in Proc. 43rd IEEE Eur.Solid State Circuits Conf. (ESSCIRC), Sep. 2017, pp. 71–74.
    4. X. Tang, B. Kasap, L. Shen, X. Yang, W. Shi, and N. Sun, “An energy efficient comparator with dynamic floating inverter preamplifier,” in Proc. IEEE Symp. VLSI Circuits (VLSI), Jun. 2019, pp. C140–C141.
    5. D. Schinkel, E. Mensink, E. Klumperink, E. van Tuijl, and B. Nauta, “A double-tail latch-type voltage sense amplifier with 18ps setup+holdtime,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, USA, Feb. 2007, pp. 314– 605.
    6.  M. Elzakker, E. vanTuijl, P. Geraedts, D. Schinkel, E. A. M. Klumperink, and B. Nauta, “A 10-bit charge-redistribution ADC consuming 1.9uWat 1MS/s,” IEEE JSSC, vol. 45, no. 5, pp. 1007– 1015, May 2010.
    7.  M. Liu, K. Pelzers, R. van Dommele, A. van Roermund, and P. Harpe, “A 106nW 10b 80kS/s SAR ADC with duty-cycled reference generation 65 nm CMOS,” IEEE JSSC, vol. 51, no. 10, pp. 2435–2445, Oct. 2016.
    8.  P.Harpe, E. Cantatore, and A. V. Roermund, “A 2.2/2.7fJ/conversionstep 10/12b 40kS/s SAR ADC with datadriven noise reduction,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, USA, Feb. 2013, pp. 270–271.
    9.  B. J. Hosticka, "Dynamic CMOS amplifiers", in JSSC 1980 vol. 15, no. 5, pp. 881-886
    10. S.-E. Hsieh and C.-C. Hsieh, “A 0.44-fJ/conversion-step 11-bit 600-kS/s SAR ADC with semi-resting DAC,” IEEE J. Solid-State Circuits, vol. 53, no. 9, pp. 2595–2603, Sep. 2018.
    11.  H.-Y. Tai, Y.-S. Hu, H.-W. Chen, and H.-S. Chen, “A 0.85 fJ/conversion step 10b 200 kS/s sub ranging SAR ADC in 40 nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2014, pp. 196–197.
    12. S.-E. Hsieh and C.-C. Hsieh, “A 0.4-V 13-bit 270-kS/s SARISDM ADC with op amp-less time-domain integrator,” IEEE J. Solid-State Circuits, vol. 54, no. 6, pp. 1648–1656, Jun. 2019.
    13. X. Tang, L. Chen, J. Song, and N. Sun, “A 1.5 fJ/conv-step 10b 100 kS/s SAR ADC with gain-boosted dynamic comparator,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2017, pp. 229–232.
    14.  T. Kobayashi, K. Nogami, T. Shirotori, and Y. Fujimoto, “A current-mode latch sense amplifier and a static power saving input buffer for low-power architecture”, VLSI Symposium, June 1992, pp. 28–29.

Recent Article