Author : Srinidhi KS 1
Date of Publication :30th August 2022
Abstract: VLSI industry has been rapidly growing where multiple processors can be implemented on a single chip. In physical design of a chip main factors to be considered are timing closure, congestion, and power. Compare to 180nm and 90nm designs were not much complicated due to less transistor density as going to lower technology nodes chip size, area, length will decrease that impact on packaging and cooling issues, so it is necessary to estimate the power at the early stage of design. Power analysis is done immediately after placement and routing stage of the chip. Power analysis can be performed in two methods one is flat method and other is hierarchical method. In flat method of analysis, the data of both top level and block level is given as input data to calculate the results whereas in hierarchical method of analysis the Power Grid View (PGV) of hierarchical block is designed which is then given as input. In hierarchical runs the sub-blocks are black boxed. The simulation is carried out using the Voltus IC Integrity Solution tool from cadence for a chip designed in 16nm FinFET technology. The results obtained from the flat method of analysis takes 2X the runtime compared to hierarchical method which would be unfavorable for very much larger circuits. The IR drop in VDD and VSS are 11.69 mW and 11.02mW respectively in flat method and 12.32 mW and 13.26 mW for VDD and VSS in hierarchical method of analysis. The accuracy is more obtained in flat run due to its transparency in logic functions.
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