Author : Monish Katari 1
Date of Publication :7th March 2017
Abstract: This paper presents an efficient hardware implementation of Convolution and Stochastic pooling algorithm. The main objective of the design is to minimize the area and power, while maximizing the throughput. Performing Convolution and Stochastic pooling in CPU consumes high amount of power and low performance relative to hardware accelerator implementation. In this paper, we propose a hardware accelerator to minimize area, power and maximize throughput. We also propose architectural techniques like Interleaving and folding to improve power and area. The optimized approach which is mapped to a 28nm ASIC target demonstrated significant power and area reduction when compared to traditional model. On the other hand, the optimized approach mapped to a FPGA target has increased source utilization when compared to conventional model.
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