Open Access Journal

ISSN : 2394-6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

ISSN : 2394-6849 (Online)

Low Power Area Efficient Flip Flop Design

Author : S Prabaharan 1 A Manikandan 2

Date of Publication :7th March 2015

Abstract: Chip density and operating frequency are increasing steadily to perform complex computations at faster rate, leading to increase in the power dissipation of digital circuit design. Low power flip flop design featuring an explicit type pulse triggered structure and a modified true single phase clock latch based on a signal feed-through scheme is presented. The proposed design acts as a solution for the long discharging path problem found in most explicit pulse triggered flip flops also achieves better speed and power performance. Proposed design outperforms the conventional pulse-triggered flip flop design in data to Q delay. The charge keeper circuit for the internal node X can be saved and a pass transistor controlled by the pulse clock is included, so input data can drive node Q directly. Along with pull up transistor, it facilitates signal driving from input source to node Q. Node can be quickly pulled up to shorten data transition delay.

Reference :

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    [2] Mahmoodi H., Tirumalashetty V., Cooke M., and Roy K. (2009) „Ultra low power clocking scheme using energy recovery and Clock gating‟ IEEE Transactions on Very Large Scale Integration Systems, Vol. 17, No. 1, pp. 33- 44.

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    [4] Shyu Y., Lin Y.M., Huang C.P., Lin C., Lin Y., and Chang Y. (2013) „Effective and Efficient approach for power reduction by using multi-bit flip flops‟ IEEE Transactions On Very Large Scale Integration Systems, Vol. 21, No. 4, pp. 624-635.

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DOI : 10.36647/ijerece/0000