Open Access Journal

ISSN : 2394-6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering
Call For Paper : Vol. 9, Issue 7 2022

ISSN : 2394-6849 (Online)

Low Power CMOS Based Dual Mode Logic Gates

Author : S SUJEETHA 1 Dr. V RANGANATHAN 2

Date of Publication :7th March 2015

Abstract: the advancement in technology and the expansion of mobile applications, power consumption has become a primary focus of attention in Very Large Scale Integration (VLSI) digital design. Recently digital sub-threshold circuit design has become a very promising method for ultra-low power applications. Circuits operating in the sub-threshold region utilize a supply voltage that comes close to or even less than the threshold voltages of the transistors, so it allows significant reduction of both dynamic and static power. A Dual Mode Logic (DML) gate, for selectable operation in either of static and dynamic modes. By scaling down the area there should be a need arise to scale down the supply voltage as well as threshold voltages of the device. It can cause static power dissipation to dominate dynamic power dissipation. To reduce the power consumption and dissipation of the circuit and increase the life time of the battery normally used in mobile phones and personal digital assistants Power Gated Sleep method can be applied. During sleep to active mode transition the stacked sleep transistors connected below the pull-down network are ON after a small duration. During the instant circuit should be experiences the Ground Bounce Noise (GBN). Inserting proper amount of delay which is less than the discharge time of the sleep transistor GBN will be reduced. The output of the circuit should be high enough to drive the another circuit. The simulations were done in TannerEDA 13.0 tool and power consumption of the proposed DML gates compared with Sleep and Dual Sleep methods in the 250-nm process.

Reference :

  1. 1. Athira P.K. and Mahalakshmi M. (2014) „Low Power Design of Dual Mode Logic using Stacking Power Gating‟, International Journal of Review in Electronics & Communication Engineering, Vol. 2, No.

    2, pp. 63- 67. 2. Kaizerman A., Fisher S. and Fish A. (2013) „Subthreshold Dual Mode Logic‟, IEEE transaction on VLSI systems, Vol. 21, No. 5, pp.979-983.

    3. Kumar M., Hussain A.Md. and Paul S.K. (2013) „New Hybrid Digital Circuit Design Techniques for Reducing Subthreshold Leakage Power in Standby Mode‟, Circuits and Systems, Vol. 4, No. 1, pp.75-82.

    4. Lakshmisree P. V. and Raghu M.C. (2014) „Design of Subthreshold Logic Gates with Power Gating Techniques‟, International Journal of Research in Engineering and Technology, Vol. 3, No. 4, pp. 174- 180.

    5. Levi I., Belenky A. and Fish A. (2014) „;Logical Effort for CMOS Based Dual Mode Logic Gates‟, IEEE transaction on VLSI Systems, Vol. 22, No. 5, pp. 1042- 1053.

    6. Nigam K.K. and Tiwari A. (2012) „Zigzag Keeper: A New Approach for Low Power CMOS Circuit‟, International Journal of Advanced Research in Computer and Communication Engineering, Vol. 1, No. 9, pp. 694-699.

    7. Reddy A.K. and Kumar S. (2013) „A Novel Technique for Ground Bounce Noise Reduction in Deep Sub Micron Circuits‟, International Journal of Innovative Technology and Research, Vol. 1, No. 5, pp.485-490.


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