Date of Publication :7th January 2015

Abstract: Significant improvements in area, delay, and power can be achieved with truncated multipliers. Fixed-width multipliers generate n-bit (instead of 2n-bit) products with low product error, but use only about half the area and less delay when compared with a standard parallel multiplier. In them, cost-effective carry-generating circuits are designed, respectively, to make the products generated more accurately and quicklyThe proposed method aims at tree reduction using proper ratio of full adders and half adders. The advantage of doing so, is experimentally we can achieve better area. The output is in the form of LSB and MSB. Using the most significant methods like reduction, deletion, truncation, rounding and final addition in order to compress the LSB part. In previous related papers, to reduce the truncation error we use error compensation circuits. But here, there is no need of error compensation circuits, and the final output is precise.

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