Author : Pauline John 1
Date of Publication :7th September 2015
Abstract: The paper describes a digital PLL circuit design as frequency synthesizer and its implementation using MULTISIM, to meet the increasing needs of high speed operation. It includes a Phase-Frequency Detector, a Loop filter, a Voltage Controlled Oscillator and a Divide by N Counter. The main aim is to decrease the power dissipation as compared with the conventional PLL. It ensures better stability, a shorter locking time and as a result, high accuracy as well as a lower sensitivity to power supply variations.
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