Author : Anitha Patibandla 1
Date of Publication :7th November 2015
Abstract: Reliability of Circuits is one of the major concerns in VLSI circuits and systems designs. Negative Bias Temperature Instability(NBTI), which has a deteriorating effect on the threshold voltage and the drive current of semiconductor devices, is emerging as a major reliability degradation mechanism .An important Reliability issue in the recent times is the Negative bias temperature instability (NBTI) in the MOS circuits in Cryptographic cores. Many works propose hardware implementations of cryptographic primitives with the promise of reduction in area, power dissipation and cost. An integrated IVCCRL approach for the reduction of Negative Bias Temperature Instability in an AES Core using the techniques of Input Vector Control (IVC) and Reversible Logic (RL) is being proposed in this paper. The effect of input vector control investigated. Mini-mum leakage vectors, which lead to minimum circuit performance degradation and maximum leakage reduction rate, are selected and used when the circuit is in the standby mode. Analysis on the potential to save the circuit performance degradation by internal node control techniques during circuit standby mode is discussed. The optimization is done for the AES algorithm using NCL Reversible Gates for low power, low cost and low area. Simulation Results have been analyzed and presented.
 V. Huard, M. Denais, and C. Parthasarathy, “NBTI degradation:From physical mechanisms to modelling,” Microelectronics Reliability, vol. 46, no. 1, pp. 1–23, 2006
 J. Stathis and S. Zafar, “The negative bias temperature instability in MOS devices: A review,” Microelectronics Reliability, vol. 46, no.2-4, pp. 270– 286, 2006.
 G. Chen, M. Li, C. Ang, J. Zheng, and D. Kwong, “Dynamic NBTI of p-MOS transistors and its impact on MOSFET scaling,” IEEE Elec. Dev. Lett., vol. 23, no. 12, pp. 734–736, 2002.
 S. Mahapatra, P. Bharath Kumar, T. Dalei, D. Sana, and M. Alam,“Mechanism of negative bias temperature instability in CMOS devices:degradation, recovery and impact of nitrogen,” in Tech. Dig.Intl. Elec. Dev. Meeting, 2004, pp. 105–108.
 S. Mahapatra and M. Alam, “A predictive reliability model for PMOS bias temperature degradation,” in Tech. Dig. Intl. Elec. Dev. Meeting, 2002, pp. 505–508.
 R. Vattikonda, W. Wang, and Y. Cao, “Modeling and Minimizationof PMOS NBTI Effect for Robust Nanometer Design,” in Proc. Of Design Automation Conference, 2006, pp. 1047–1052.
 S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, “An Analytical Model for Negative Bias Temperature Instability,” in IEEE/ACM Intl. Conf. on ComputerAided Design, 2006.
 S. Kumar, C. Kim, and S. Sapatnekar, “Impact of NBTI on SRAM Read Stability and Design for Reliability,” in Intl. Symp. on Quality Electronic Design, 2006, pp. 210–218.
 B. Paul, K. Kang, H. Kufluoglu, M. Alam, and K. Roy, “Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits,” in Proc. of Design, Automation and Test in Europe, vol. 1, 2006, pp. 1–6.
 A. Abdollahi, F. Fallah, and M. Pedram, “Leakage current reduction in CMOS VLSI circuits by input vector