Author : Sana Afreen 1
Date of Publication :7th January 2016
Abstract: Comparator is one of the basic building blocks of analog to digital converter. The need for ultra-low-power, area efficient and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to improve speed and efficiency of power. In this paper, an analysis on the delay of convectional dynamic single Tail comparator, Double Tail Comparator and double tail comparator for low power will be presented. The sub threshold leakage of transistors has usually been very small in the off state, as gate voltage is below threshold. But as voltages have been scaled down with transistor size, sub threshold leakage has become a considerable factor. Hence, to reduce the sub threshold leakage a new CMOS dynamic comparator using conventional CMOS inverter and switches method is proposed. The circuit has a dual input single output differential amplifier which is suitable for high speed analog to digital converters with improved speed and low power dissipation. The simulation results confirm the analysis and show that in the proposed dual tail dynamic comparator both power consumption and delay time are significantly reduced even in small supply voltage.. The simulation results will be shown in Mentor Graphics.
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