Open Access Journal

ISSN : 2394-6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

ISSN : 2394-6849 (Online)

Design And Development Of ARINC 717 Protocol

Author : Smitha M R 1 Aparna 2

Date of Publication :7th February 2016

Abstract: ARINC has provided leadership in developing specifications and standards for avionics equipment, and one of the standard protocol used for communication bus is ARINC 717. This communication occurs between Digital flight data acquisition unit (DFDAU) and Digital flight data recorder (DFDR). The basic unit of information defined by the ARINC 717 protocol is a 12- bit word. The Programmable bit rates of ARINC 717 are 384, 768, 1536, 3072, 6144, 12288, 24576, 49152 and 98304 bits/sec (32, 64, 128, 256, 512, 1024, 2048, 4096 and 8192 words/sec). The data is serially transmitted in ARINC 717. The top level architecture of the ARINC 717 protocol has 4 modules ARINC 717 transmitter, ARINC 717 receiver, Transmit and Receive 32*12-bit FIFO to store and fetch the data, and ARINC 717 clock generation. In this proposed work a Hardware Descriptive Language (HDL) based design and development of the ARINC 717 protocol for standard data bus communication. The input data is taken from Digital flight data acquisition unit. This continuous data stream is stored in a 32*12-bit FIFO. The encoder module at ARINC 717 transmitter converts a continuous data stream into a 12 bit encoded Harvard Bi-Phase (HBP) format which are then encoded to form ARINC 717 frames. This encoded data is decoded using both Harvard bi-phase and bi-polar return to zero at the receiver. The decoded data is stored in the Receive FIFO. Then the continuous stream of output data is taken for recording in Digital flight data recorder. The design and development is done using Xilinx software.

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DOI : 10.36647/ijerece/0000