Author : S.M.Dinesh 1
Date of Publication :7th April 2016
Abstract: Power consumption has become a crucial concern in today’s VLSI system style. The growing marketplace for quickfloating purpose coprocessors, digital signal process chips, and graphics processor has created a requirement for topspeed and space economical multipliers. A Wallace tree multiplier factor may be a improved version tree based mostly multiplier factor design. It uses carry save addition rule to cut back the latency. This paper aims at extrareduction of latency and power consumption of the Wallace tree multiplier factor. The simulation has been meted outmistreatment the Xilinx ISE tool.
Reference :
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