Author : Reshma P Vengaloor 1
Date of Publication :7th April 2016
Abstract: In this paper, a Bidirectional Network on Chip (BiNoC) using flit level speed up scheme ( FSNoC) is proposed for enhancing the performance of on chip communication, by optimizing the available bandwidth. To achieve this goal, a flit level speed up scheme using self reconfigurable bidirectional channel is developed. For interrouter bandwidth utilization, a distributed channel configuration scheme is developed, which dynamically changes the link direction. Intrarouter bandwidth utilization is possible by allowing multiple flits from same packet to use the idle channel bandwidth. In this way the effective channel bandwidth between two routers can change adaptively depending on the network traffic. An input buffer architecture, which supports reading /writing two flits from/to same virtual channel at the same time and a switch allocator for supporting the flit level parallel arbitration, is also designed. A virtual cut through routing is used for router design, which helps to reduce the packet delay and the memory requirement. So the data to be transferred is divided into flits of equal size. Routing decisions for flits are made by using XY routing algorithm. FSNoC provide better bandwidth utilization, low latency and reduction in area occupancy. FSNoC is designed using VHDL language and synthesized in Xilinx ISE Design Suit 13.2 and it is simulated in Model Sim SE 6.3f.
Reference :
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