Date of Publication :7th April 2016

Abstract: In modern electronic systems, as the computing requirement increase, more and more intellectual property (IP) cores are embedded in System-On-Chip (SOC). On-chip communication architectures play an important role in determining the over-all performance of SOC designs. Communication architectures should be flexible so as to offer high performance over a wide range of traffic characteristics. The modern communication protocol, AXI (Advanced eXtensible Interface) supports advanced transactions like out-of-order transactions that improve communication efficiency. However a deadlock situation may occur if these transactions are not handled properly. The deadlock may get occurred if each master in a set of masters is holding a slave and waiting for another slave held by another master in the set. Hence a bus architecture avoiding deadlock condition, based on AXI protocol has to be developed. The masters and the slaves communicate each other through the AXI interconnect having different channels. The address bits should be transmitted initially through the address channel and data will be transmitted after that through the data channel. The encoding and decoding of the data bits are done using DMC (Decimal Matrix Codes). For avoiding deadlock, a waiting relation detector can be used to find whether any waiting relation exists. Thus multiple transactions can be handled without any deadlock occurrence. The designing language is VHDL and synthesis in Xilinx ISE Design Suite 13.2 and can be simulated in ModelSim SE 6.3f.

Reference :