Date of Publication :7th April 2016

Abstract: As a result of increased demand for on chip communication bandwidth due to multi core chips, packet switched network on chip (NoC) has been emerged as a replacement of bus based on chip interconnects. This work represents a globally asynchronous locally synchronous (GALS) NoC architecture with hard real time multiprocessor platform.It is a special NoC architecture, which uses statically scheduled time division multiplexing (TDM) to control the communication over a structure of routers, links and network interfaces to offer real time guarantees. It also manages the pipelined data maintenance, storage mechanism as well as transfer of data bits from one local memory to another. The router in the architecture uses source routing along with an efficient TDM scheme which does not need any flow control, arbitration and buffering. Also it uses a two phase bundled data handshake latches based on the mousetrap latch controller with a gating mechanism to reduce the energy consumption. The network interface(NI) in the architecture consist of a direct memory access (DMA ) controller which avoid the need of synchronization. NI plays an important role in the end to end data transfer between two communicating processor cores. The work is coded by using verilog and is simulated by Xilinx ISE 13.2.

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