Author : Anumol Thomas 1
Date of Publication :7th April 2016
Abstract: Error correction provides reliable information free from errors. BCH codes are widely used to perform error correction. However, in order to improve the reliability of error correction BCH codes have been replaced by Low Density Parity Check (LDPC) codes. LDPC codes are special class of error correcting codes widely used in communication and memory systems, due to its Shannon limit approaching performance and favorable structure. A sub class of LDPC codes, called Quasi-Cyclic (QC) LDPC codes is used as the error correcting code due to their structured Parity Check Matrices (PCM). These codes are flexible in the sense of supporting wide range of code lengths and rates. This work deals with an efficient byte reconfigurable, high throughput QC-LDPC codec design. The codec is able to support multiple bits with the constraint that size of the sub-parity matrix be multiples of eight. Error detection is done using modified majority logic decoding. Majority logic decoding is preferred as they can correct large number of errors having even as well as odd number of bit flips. This method reduces the decoding time by detecting errors up to four bit-flips in first three iterations of decoding. If no error is detected decoding terminates without completing rest of the iterations, thereby reducing the average decoding time.
Reference :
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[1] Yu-Min Lin, Huai-Ting Li, Ming-Han Chung, and AnYeu (Andy) Wu,”Byte-Reconfigurable LDPC Codec Design With Application to High-Performance ECC of NAND Flash Memory Systems”, IEEE Trans. Circuits Syst. I: REGULAR PAPERSVOL. 62, NO. 7, July 2015
[2] Y. Kou, S. Lin, and M. P. C. Fossorier, Low density parity-check codes based on finite geometries: a rediscovery and new results, Inform. Theory, via IEEE, May 2015.
[3] Y. S. Park, Y. Tao, and Z. Zhang, A fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating, IEEE J. Solid-State Circuits, vol. 50, no. 2, pp.464475, Feb. 2015.
[4] J. Li, K. Zhao, J. Ma, and T. Zhang, Realizing unequal error correction for nand flash memory at minimal read latency overhead, IEEE Trans. Circuits Syst. II, Exp.Briefs, vol. 61, no. 5, pp. 354358, May 2014.
[5] Shih-Fu Liu, Pedro Reviriego and Juan Antonio Maestro Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications, IEEE Trans On Vlsi Systems, Vol. 20, No.1, Jan 2012
[6] Y. H. Chien, M. K. Ku, and J. B. Liu, Low-complexity iteration control algorithm for multi-rate partially parallel layered LDPC decoders, IET Electron. Lett., vol. 48, no. 22, pp. 14061407, Oct. 2012.
[7] S. Kim, G. E. Sobelman, and H. Lee, A reduced complexity architecture for LDPC layered decoding schemes, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 6, pp. 10991103, Jun. 2011.
[8] X. Y. Shih, C. Z. Zhan, C. H. Lin, and A. Y.Wu, An 8.29 52mW multi-mode LDPC decoder design for mobile WiMAX system in 0.13 CMOS process, IEEE J. SolidState Circuits, vol. 43, no. 3, pp. 672683, Mar. 2008
[9] N. Mielke, T. Marquart, N. Wu, J. Kessenich, H. Belgal, E. Schares, F. Trivedi, E. Goodness, and L. R. Nevill, “Bit error rate in NAND flash memories,” in Proc. IEEE Int. Rel. Phys. Symp., Apr. 2008, pp. 9–19.
[10]Z. W. Li, L. Chen, L.-Q. Zeng S. Lin, andW. H. Fong, Efficient encoding of quasi-cyclic low-density paritycheck codes, IEEE Trans. Commun., vol. 54, no. 1, pp. 7181, Jan. 2006.
[11]M. M. Mansour, A turbo-decoding message-passing algorithm for sparse paritycheck matrix codes, IEEE Trans. Signal Process., vol.54, pp. 43764392, Nov. 2006
[12]M.C. Davey and D.J.C. MacKay, Low-density parity check codes over GF(q), IEEE Commun. Lett., vol. 2, no. 6, pp. 165-167, Jun. 1998.