Author : Sinam Ajitkumar Singh 1
Date of Publication :7th April 2016
Abstract: CRC is the most powerful tools for detecting and correcting error in data transmission. CRC can be implemented in hardware using Linear Feedback Shift Register. This paper emphasizes mainly on data transmission using Ethernet. Serial CRC can be implemented easily but it cannot achieve high speed. Using F matrix algorithm, Parallel CRC can be implemented, in which speed is drastically increased. While transmitting 64-bit data using serial CRC-32, an output is obtained after 64 clock cycle. However, using Parallel CRC-32 output is obtained after 9 clock cycle, which required 50% less cycles to generate CRC compared to serial CRC generator. The design method is employed with Xilinx ISE 9.2 Tool
Reference :
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[1] G. Campobello, G. Patane, Marco Russo, "Parallel CRC Realization," IEEE Transactions on Computers, Vol 52, No.10, pp.1312-1319,Oct.2003.
[2] Yan sun and Min Sik Kim, "High Performance TleBased Algorithm for Pipelined CRC Calculation," Consumer Communication and Networking Conference (CCNC), 7th IEEE, Vol. No. pp. 1-2, 9-12 Jan 2010.
[3] Weidong Lu and Stephan Wong, "A Fast CRC Update Implementation," IEEE Workshop on High Performance Switching and Routing, pp. 113-120, Oct 2003.
[4] F Barun and M. Waldvogel,"Fast Incremental CRC Updates for IP over ATM Networks," IEEE Workshop on High Performance Switching and Routing. Vl. No. pp. 48- 52, 2001.
[5] Albertengo. G and Sisto. R, "Parallel CRC Generation," Micro, IEEE Vol. No.5 pp. 1312-1319, Oct 2003.
[6] W. W. Peterson and D.T. Brown, "Cyclic codes for error detection," Proceedings of the IRE, Vol. 49, No.1, pp. 228-235, Jan 1961.
[7] M. Spachmann, “Automatic Generation of Parallel CRC Circuits,” IEEE Design and Test of Computers, May 2001