Author : Spoorthi Y 1
Date of Publication :7th May 2016
Abstract: In nanometer scale static-RAM (SRAM) arrays, systematic inter-die and random within-die variations in process parameters can cause significant parametric failures, severely degrading parametric yield. In this paper, we investigate the interaction between the inter-die and intra-die variations on SRAM read and write failures. To improve the robustness of the SRAM cell, we propose closed-loop adaptive compensation algorithms that directly sense the global read stability and writ ability of the cell. The main aim of the of the proposed scheme is to design a sensor that directly sense the global read stability and writ ability of an SRAM die and apply proper cell correction/compensation mechanism using cell and peripheral supply voltages to mitigate the dominant type of failure. Since the direct sensing of the global read stability and write-ability helps to successfully distinguish global corners of nMOS and pMOS devices, the proposed scheme becomes more effective in reducing the parametric failures.
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