Author : Jamuna R K 1
Date of Publication :7th May 2016
Abstract: Router is an essential component of Network-on-Chip(NoC). Conventionally used homogeneous router provide good throughput but buffer slots are fixed and cannot be reconfigured to the requirement. Here it consumes more power as not all the buffer slots are used. To overcome this drawback, reconfigurable router is designed where in the buffer slot size can be varied. That is buffer slots in each channel can be used by other channels. This utilizes the router resources efficiently there by reducing the power consumption when compared to homogeneous. The homogeneous router is designed with 16 buffer slots and reconfigurable router with 4 buffer slots which are simulated using Xilinx 14.7. Power is calculated using Xpower Analyzer where reconfigurable router is consuming 2.13mW less power compared to homogeneous router.
Reference :
-
[1] L. Benini and G.D. Micheli, ―Network on chips: a new SoCs paradigm,‖ IEEE Computer, vol. 35, no. 1, pp. 70–78, Jan. 2002.
[2] J. U. Duncombe, ―Infrared navigation—Part I: An assessment of feasibility,‖ IEEE Trans. Electron Devices, vol. ED-11, pp. 34-39, Jan. 1959.
[3] M. Vestias and H. Neto, ―Router design for application specific network-on-chip on reconfigurable systems,‖ Field Program. Logic Appl, vol. 1, pp. 389– 394, 2007.
[4] B. Ahmad, A. Ahmadinia, and T. Arslan, ―Dynamically reconfigurable NoCs with bus based interface for ease of integration and reduced designed time,‖ in Proc. NASA/ESA Conf. Adapt. Hardw. Syst. (AHS), pp. 309–314, 2008.
[5] S. Sahu and H. M. Kittur, ―Area and power efficient network on chip router architecture,‖ IEEE Conference on Information and Communication Technology (ICT), pp. 855-859, April 2013.
[6] A. Bhanwala, M. Kumar, Y. Kumar, ―FPGA based Design of Low Power Reconfigurable Router for Network on Chip(NoC),‖ International Conference on Computing, Communication and Automation (ICCCA2015), PP. 1320-1326, 2015.
[7] D. Matos, C. Concatto, M. Kreutz, F. Kastensmidt, L. Carro and A. Susin, ―Reconfigurable routers for low power and high performance,‖ IEEE Transaction on Very Large Scale Integration (VLSI) System, vol. 19, no. 11, pp. 2045-2057, Nov. 2011.
[8] C. Xuning and L. Peh, ―Leakage power modeling and optimization in interconnection networks,‖ in Proc. Int. Symp. Low Power Electron. Des. (ISLPED), 2003, pp. 90–95.
[9] L. Manferdelli, N.K. Govindaraju and C. Crall, ―Challenges and opportunities in many-core computing,‖ Proc. IEEE, vol. 96, no. 5, pp. 808–815, May 2008.
[10]K. Srinivasan and K.S. Chatha, ―A low complexity heuristic for design of custom network-on-chip architectures,‖ in Proc. Des., Autom. Test Euro. Conf., vol. 1, pp. 1–6, 2006.