Author : Basavaraj Mirji 1
Date of Publication :7th May 2016
Abstract: In current scenario, computing system of microprocessor involves data comparison circuit for matching input data to the stored data in memory. For protection of data and to improve reliability, the recent microprocessor uses error correcting code. In this paper a new architecture for data matching is presented to reduce the delay and hardware circuit complexity. Taking into account the property of the systematic codeword, the deliberate shape comprising of information and parity bits independently, so parallel examination of information and parity bits diminishes the delay of the overall circuit.
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