Open Access Journal

ISSN : 2394 - 6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

ISSN : 2394-6849 (Online)

ASIC Implementation of Data Comparison Circuit for Cache Memory

Author : Basavaraj Mirji 1 R Pramod 2 Dr. V. Anandi 3

Date of Publication :7th May 2016

Abstract: In current scenario, computing system of microprocessor involves data comparison circuit for matching input data to the stored data in memory. For protection of data and to improve reliability, the recent microprocessor uses error correcting code. In this paper a new architecture for data matching is presented to reduce the delay and hardware circuit complexity. Taking into account the property of the systematic codeword, the deliberate shape comprising of information and parity bits independently, so parallel examination of information and parity bits diminishes the delay of the overall circuit.

Reference :

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    [2] Wei Wu, D Somasekhar, Shih.-Lien Lu “Direct compare of information coded with error correcting codes”, IEEE Trans. Very Large Scale Integr. Syst., vol. 20, no. 11, pp. 2147–2151, Nov. 2012.

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    [5] Y. Lee, H. Yoo, I. C. Park “6.4Gb/s multi threaded BCH encoder and decoder for multi channel SSD controllers,” in ISSCC Dig. Tech. Papers, 2012, pp. 426- 427.

    [6] S. Lin, D. J. Costello, “Error Control Coding Fundamentals and Applications”, 2nd ed. Englewood Cliffs, NJ, USA: Prentice-Hall, 2004.

    [7] Caxton C, Foste, Fred D. Stockan, “Counting Responders in an Associative Memory”, IEEE Transactions on computer, December 1971.

    [8] Brown, Frank M, “Weighted Realizations of Switching Functions”, IEEE transactions on computer, December 1975.


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