Author : Sumaiyya Fatima Ghouri 1
Date of Publication :7th May 2016
Abstract: The new prototype for clock distribution that utilizes current, instead of the voltage, to disperse a global clock signal with decreasing power utilization. While current mode (CM) signaling has been utilized as a part of balanced signs, this is the prime use in a one-to - numerous clock appropriation systems. To perform this, we make another best current-mode pulsed flip-flop with enable (CMPFFE) utilizing 45 nm CMOS technology. The power is global transports, clock distribution network (CDN), and synchronous signs by and large. The clock distribution system devours the extensive measure of power in synchronous computerized frameworks. Clock distribution systems are the key component of a synchronous and non- synchronous advanced circuit and a huge power. At the point when the CMPFFE is consolidated with a CM transmitter, the main CM clock dispersion system shows lower normal power contrasted with conventional voltage mode.
Reference :
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1) H. Zhang, G. Varghese, and J. M. Rabaey, “Low swing on- chip sig-naling techniques: Effectiveness and robustness,” IEEE Trans. VeryLarge Scale Integr. (VLSI) Syst., vol. 8, no.3, pp. 264–272, Jun. 2000.
2) A. Katoch, H. Veendrick, and E. Seevinck, “High speed current-mode signaling circuits for on-chip interconnects,” in Proc. ISCAS, May 2005, pp. 4138– 4141.
3) M. R. Guthaus, G. Wilke, and R. Reis, “Revisiting automatedphysical synthesis of high-performance clock networks,”ACM Trans. DesignAutom. Electron. Syst., vol. 18, no. 2, pp.31:1–31:27, Apr. 2013.
4) M. Yamashina and H. Yamada,“AnMOS current mode logic (MCML) circuit for low-power sub-GHz processors,” IEICE Trans. Electron., vol. E75-C, no. 10, pp. 1181–1187, 1992.
5) F. Yuan, Cmos Current-Mode Circuits for Data Communications. New York: Springer, Apr. 2007. NCSU, FreePDK45 [Online]. Available: http://www.eda.ncsu.edu/ wiki/FreePDK45
6) R. Islam and M. Guthaus, “Current-mode clock distribution,”in Proc.ISCAS, Jun. 2014, pp. 1203–1206