Open Access Journal

ISSN : 2394 - 6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

ISSN : 2394-6849 (Online)

Low Power Flip Flop Implemented Using Transmission Gates and Feed through Logic

Author : Arshi Kahkaishan 1 Rekha S 2

Date of Publication :7th May 2016

Abstract: in this paper, a low-power flip-flop (FF) design featuring an explicit type pulse-triggered structure and a modified true single phase clock (TSPC) latch based on a signal feed-through scheme is presented. This paper solves the long discharging path problem in conventional explicit type pulse-triggered FF (MHLFF) design. An advanced simulation which targets to achieves better speed and power performance. Reducing redundant switching activity has a good impact on reducing power dissipation. CMOS 90nm technology have been used to implement simulation results. The maximum power saving is achieved as compared to the previous design. H-SPICE tool is used for simulation purpose.

Reference :

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    [4] B. Kong, S. Kim, and Y. Jun, “Conditional-capture flip-flop for statistical power reduction,” IEEE J. Solid-State Circuits, vol. 36, no. 8, pp. 1263–1271, Aug. 2001.

    [5] S. H. Rasouli, A. Khademzadeh, A. Afzali-Kusha, and M. Nourani, “Low power single- and double-edge triggered flip- flops for high speed applications,” IEE Proc. Circuits Devices Syst., vol. 152, no. 2, pp. 118– 122, Apr. 2005.

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