Author : Arshi Kahkaishan 1
Date of Publication :7th May 2016
Abstract: in this paper, a low-power flip-flop (FF) design featuring an explicit type pulse-triggered structure and a modified true single phase clock (TSPC) latch based on a signal feed-through scheme is presented. This paper solves the long discharging path problem in conventional explicit type pulse-triggered FF (MHLFF) design. An advanced simulation which targets to achieves better speed and power performance. Reducing redundant switching activity has a good impact on reducing power dissipation. CMOS 90nm technology have been used to implement simulation results. The maximum power saving is achieved as compared to the previous design. H-SPICE tool is used for simulation purpose.
Reference :
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[1] R. Singh, N.Sigroha, R. Rohila, B. Krishan, “Low power pulse triggered flip flop design with modified conditional pulse enhancement scheme,” International Journal for Scientific Research & Development, vol. 3, issue 01, ISSN (online): 2321- 0613, 2015.
[2] Bhargavaram.D and Pillai, M.,”low power dual edge triggered flipflop”.in Advance Engineering, science and Management (ICAESM),International Conference on IEEE,(2012),63-67.
[3]. M.-W. Phyu, W.-L. Goh, and K.-S. Yeo, “A lowpower static dual edge triggered flip-flop using an output-controlled discharge configuration,” in Proc. IEEE Int.Symp. Circuits Syst., May 2005, pp. 2429– 2432.
[4] B. Kong, S. Kim, and Y. Jun, “Conditional-capture flip-flop for statistical power reduction,” IEEE J. Solid-State Circuits, vol. 36, no. 8, pp. 1263–1271, Aug. 2001.
[5] S. H. Rasouli, A. Khademzadeh, A. Afzali-Kusha, and M. Nourani, “Low power single- and double-edge triggered flip- flops for high speed applications,” IEE Proc. Circuits Devices Syst., vol. 152, no. 2, pp. 118– 122, Apr. 2005.
[6] P. Zhao, T. Darwish, and M. Bayoumi,“Highperformance and low power conditional discharge flip-flop ,” IEEE Transaction on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 5, pp. 477- 484,May 2004.