Author : Devikarani H S 1
Date of Publication :7th May 2016
Abstract: This paper proposes the Field Programmable Gate Array (FPGA) architecture implementation of reconfigurable RootRaised Cosine (RRC), Finite Impulse Response (FIR) filter in which all the adders present in the designed filter are replaced by the modified Carry-Select Adders (CSLA), which is mostly used in Digital Up Converter (DUC). The proposed filter can be reconfigured with one of three different interpolation factors of 4, 6, and 8 for 25, 37, and 49-taps filters respectively and one of two roll-off factors. The basic element of a filter is multiplier and 2-bit Binary Common Sub expression Elimination (BCSE) algorithm is used in the design of the multiplier in this work. It is a two-step optimization technique of designing a reconfigurable VLSI architecture of interpolation filter to reduce the number of slices required for the filter. The maximum operating frequency analysis is carried out using Xilinx Synthesis Tool (XST) and Cadence software.
Reference :
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