Author : Kavya Shree M S 1
Date of Publication :7th May 2016
Abstract: As the demand increases for low power dissipation in digital computing system, a new technique called Reversible Logic was introduced. Reversible logic is one of the promising field which solves the problem of power dissipation and also it is the basic requirement for the field of quantum computing. The multiplication which plays a prior role in DSP applications. Some of the important operations in DSP are filtering, convolution and inner partial products. These are the processes which requires multipliers so the speed and performance of their operations depends on the speed of the multiplication and addition. The logarithmic multiplier which is designed based on the Mitchell’s Algorithm proposed by Mitchell. The logarithmic multiplier convert multiplication and division problem into addition and subtraction.. This paper gives the design of pipelined iterative logarithmic multiplier using reversible logic.
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