Open Access Journal

ISSN : 2394 - 6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

ISSN : 2394-6849 (Online)

An Efficient Design of Dynamic VITERBI Decoder Architecture

Author : Mr.Parsekar Gaurav Rajanikant 1 Mrs.Veena H.S 2 Mr.Girish G Satardekar 3

Date of Publication :7th June 2016

Abstract: The emerging applications of wireless networks enforce new challenges in design of algorithms and communication protocols. In such scenario of challenges, coding for error control has be- come extremely important to provide robust communication and maintain quality of service. One method to improve Bit Error Rate (BER) while maintaining high data reliability, is to use an error correction technique like the VITERBI algorithm. The VITERBI algorithm provides an efficient method for Forward Error Correction (FEC) that improves channel reliability. As constraint length associated with input bits increases it needs to implement it with lesser computations and lesser hardware to decode the original data. Therefore Dynamic VITERBI Algorithm is used for decoding which reduces error probability, computation and employ lesser hard- ware with increased speed. The purpose of this paper is to understand VITERBI Algorithm, Adaptive VITERBI Algorithm and to find the alternative to shortcomings in the design and implement the idea on a hardware.

Reference :

  1. [1] T. Kalavathidevi and C. Venkatesh, “Area Efficient Low Power VLSI Architecture for A VITERBI Decoder Using Gate Diffusion Input(GDI) Logic Style”, European Journal of Scientific Research, Vol. 49, no.4, pp. 521-532, March 2011.

    [2] C. Arun and P. Rajamani, “Design and VLSI imple mentation of a low probability of error VITERBI decoder,” First international conference on Emerging trends in Engineering and technology, pp. 418-423, 2008.

    [3] T. Gemmeke, V. S. Gierenz, and T. G. Noll, “RTL implementation of VITERBI decoder,” Dept. Of Computer Engineering, IEEE Transactions on circuits and systems, June 2006.

    [4] S. Swaminathan, R. Tessier, D. Goeckel, and W. Burleson, “A dynamically reconfigurable adaptive VITERBI decoder,” Monterey, California, USA, February 24-26, 2002

    [5] Mahender Veshala,Tualsagari Padmaja,Karthik Ghanta, “FPGA Based Design and Implementation of Modified VITERBI Decoder for a Wi-Fi Receiver,” IEEE Conference on Information and Communication Technologies (ICT 2013) ,2013.


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