Author : Aravind R 1
Date of Publication :7th June 2016
Abstract: Dynamic logic style is used in high performance circuit design because of its fast speed of operation and less number of transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and consuming very less power as compared to other proposed circuit. In this paper we have proposed a novel circuit for domino logic which has less area and has less power-delay product (PDP) as compared to previous reported articles. Low PDP is achieved by using semidynamic logic buffer and also reducing leakage current when PDN is not conducting. Then comparison analysis has been carried out by simulating the circuits in 90nm CMOS process technology from TSMC using Tanner EDA 14.11.
Reference :
-
[1] F. Mendoza-Hernandez, M. Linares-Aranda and V. Champac,“Noise tolerant improvement in dynamic CMOS logic circuit”,IEEE Proc.- Circuits Devices Systems, Vol 153, No. 6, Dec 2006,pp.. 565-573.
[2] Krambeck, R.H., Lee, C. M., and Stephen Law, H.-F., “High-speed compact circuits with CMOS”, IEEE J. SolidState Circuits, 1982, 17, (3), pp. 614–619.
[3] H.L. Yeager et al, “Domino Circuit Topology”, U. S. Patent 6784695, Aug. 31, 2004.V.
[4] Oklobdzija, V.G., and Montoye, R.K., “Designperformance tradeoffs in CMOS domino logic”. Proc. IEEE Conf. on Custom Integrated Circuits, May 1985, pp.. 334–337V.
[5] Mahmoodi-Meimand H., Roy K.: „Diode-footed domino: a leakagetolerant high fan-in dynamic circuit design style‟. IEEE Trans Very Large Scale integration Syst 2004 51(3) PP. 495-503.
[6] M. C. Johnson, D. efficient use Somasekhar, L. Y. Chiou, and K. Roy, (2002) “Leakage control with efficient use of transistor stacks in single threshold CMOS”, IEEE Trans. VLSI Syst., Vol. 10, pp. 1 –5.
[7] A. Alvandpour, R. Krishnamurthy, K. Sourrty, S.Y. Borkar, A sub- 130-nm conditional-keeper technique, IEEE Journal of Solid State Circuits 37 (2002) 633–638.
[8] Z. Liu, V. Kursun, Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current, Elsevier: Microelectronics Journal 37 (2006) 812–820.
[9] V. Sharma, W.K. Al-Assadi, “Analysis and Modeling of Crosstalk Noise in Domino CMOS Circuits,” IEEE Region 5 Technical Conference, pp.374, April 2007.
[10] Song Jia, Fei Liu, Jun Gao, Ling Liu, Xinan Wang, Tianyi Zhang, Zhongjian Chen, Lijiu Ji, “A 64-bit look ahead carry chain in Inverted- Domino logic,” IEEE Conference on Electron Devices andSolid-State Circuits, pp.281, Dec. 2000
[11] S. M. Kang, Y. Leblebici, „CMOS Digital Integrated Circuits: Analysis & Design‟, TATA McGraw- Hill Publication, 3e, 2003.
[12] K.S. Yeo, K. Roy, „Low- Voltage, Low-Power VLSI Subsystems‟.