Open Access Journal

ISSN : 2394-6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

ISSN : 2394-6849 (Online)

FPGA Implementation of Distributed Canny Edge Detector for Low Clarity Images

Author : Rinjo A J 1 Remya K P 2

Date of Publication :7th July 2016

Abstract: Edge detection is the most common preprocessing step in many image processing algorithms. Edge detection is the method to find the image brightness changes sharply or, more formally, has discontinuities. The points at which image brightness changes sharply are typically organized into a set of curved line segments termed edges. The purpose of edge detection is to reduce the data in an image. Canny detector has high latency, because itís a frame level processing. So in order to avoid that problem new canny edge detection developed. Itís a block level processing. The entire image divides into block. In the original canny compute the high and low threshold values based on the frame level.. In the new distributed canny detector have a histogram, which helps to give more clarity to the image. The synthesis tool used here is Xilinx ISE 14.2. Using hardware description language (Verilog) the system can implement on Spartan 6 FPGA.

Reference :

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