Date of Publication :7th July 2016

Abstract: The binary adder is a critical element in the most digital circuit design including the digital signal processors (DSP) and the microprocessor data path units. As such as extensive research that continues to be focused on improving power delay performance of an added. This paper proposes new technology for implementing the low power full adder by using a set of Gate Diffusion Input (GDI) cell based multiplexers. Full adder is the very common example of combinational circuits and is most widely used in the Application Specific Integrated Circuits (ASICs). It is always advantageous to have low power action for sub components that can be used in VLSI chips. The explored technique of this realization achieves a low power high speed design for the widely used sub component full adder. Simulated outcome using state of art simulation tool represents very finer behavioral performance of a projected method over standard CMOS based full adder approach. Power, area and speed comparisons between conventional and proposed full adder are also presented.

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