Open Access Journal

ISSN : 2394 - 6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

ISSN : 2394-6849 (Online)

Implementation of Ternary Logic Gate

Author : P.Koti Lakshmi 1 A. Swathi 2 Prof. Rameshwar Rao 3

Date of Publication :7th August 2016

Abstract: A ternary logic system was first proposed by the polish mathematician Jan Lukasiewicz, in 1920.The ternary circuits developed are shown to have some significant advantages relative to other known binary circuits like low power dissipation, and reduced propagation delay and component count. Nevertheless, the associated reduction in the word length in the case of the ternary circuits tends to alleviate to a large extent the pin limitation problem associated with VLSI implementation. In this paper the basic gate implementation is considered and the power requirements for different methods of realization was studied.

Reference :

  1. 1. HURST, S.L: “Multiple-Valued Logic- Its status and its future”, IEEE Trans.,1984, c-33,(10),pp.1160-1179.

    2 .Ms.Nilmani P.wanjari, Ms.Shweta P.Hajare “VLSI Design and Implementation of Ternary Logic Gates and Ternary SRAM Cell”,IJECSE.

    3. R. Mariani, F. Pessolano, R. Saletti “A New CMOS Ternary Logic Design for Low-power Low-voltage Circuits”

    4. A.P.Dhande, sathish s.Narkhede, shridar s.Dudam“VLSI Implementation of Ternary Gates using tanner tool”. 2014. Khushdeep kaur, Preetisingh, Gaimajoshi “Analysis of ternary multiplier using Booth encoding technique” 2015


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