Author : Swathi Samanthapudi 1
Date of Publication :7th August 2016
Abstract: The requirement to hold up different digital signal processing (DSP) and classification applications on energyconstrained devices has regularly developed. This applications usually execute matrix multiplications using fixed-point arithmetic , while indicating tolerance for some counting errors. Hence, improving the energy efficiency of multiplications is critical. In this brief, we introduce multiplier architectures that can tradeoff counting accuracy with energy consumption at design time. Compared with a actual multiplier, the suggested multiplier can consume 57% lower energy/op with average counting error of ?1%. Absolutely, we signify such a little counting error does not particularly failure the effect of DSP and the preciseness of classification applications.
Reference :
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[1] Srinivasan Narayanamoorthy, Hadi Asghari Moghaddam, Zhenhong Liu, Taejoon Park, and Nam Sung Kim, July 2014, “Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Early Access Articles, pp. 1 – 5.
[2] R. K. Krishnamurthy and H. Kaul, “Ultra-low voltage technologies for energy-efficient special-purpose hardware accelerators,” Intel Technol. J., vol. 13, no. 4, pp. 102–117, 2009.
[3]R. Hegde and N. R. Shanbhag, “Energy-efficient signal processing viaalgorithmic noise-tolerance,” in Proc. IEEE/ACM Int. Symp. Low Power Electron. Design (ISLPED), Aug. 1999, pp. 30–35.
[4] D. Menard, D. Chillet, C. Charot, and O. Sentieys, “Automatic floatingpoint to fixed-point conversion for DSP code generation,” in Proc. ACM Int. Conf. Compilers, Archit., Syn. Embedded Syst. (CASES), 2002,pp. 270–276.
[5] V. K. Chippa, D. Mohapatra, A. Raghunathan, K. Roy, and S. T. Chakradhar, “Scalable effort hardware design: Exploiting algorithmic resilience for energy efficiency,” in Proc. 47th IEEE/ACM Design Autom. Conf., Jun. 2010,pp. 555–560.
[6] D. Mohapatra, G. Karakonstantis, and K. Roy, “Significance driven computation: A voltage-scalable, variation-aware, quality-tuning motion estimator,” in Proc. 14th IEEE/ACM Int. Symp. Low Power Electron. Design (ISLPED), Aug. 2009, pp. 195–200.
[7] C. H. Chang and R. K. Satzoda, “A low error and high performance multiplexer-based truncated multiplier,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 12, pp. 1767–1771, Dec. 2010