Author : P. Ravi Kumar 1
Date of Publication :7th August 2016
Abstract: A Programmable Frequency Divider (PFD) is proposed in this paper. First the number of inputs for PFD are increased by using asynchronous counter ,reload generator and duty cycle correction circuit`s. Second the area of PFD is reduced using standard cell layout technology. This design is implemented with 0.9volts power supply,it can be operated from 1MHz to 2GHz and the division ratio ranges from 1 to 511 at 1.25 GHz of input clock and output duty cycle ranges from48.47 to 52.22, the total power consumption of proposed programmable frequency divider is only 0.176 mW at 1.25GHz and active die area 0.000048204 mm2 .
Reference :
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