Date of Publication :7th October 2016

Abstract: In current scenario, VLSI circuit’s greatest challenges is to reduce the power dissipation and surface area so that longer life and high performance achieved to greater extent. The key parameter is threshold voltage to reduce the leakage power. In our proposal, we design low power and high performance JK flip-flop. JK flip-flop is designed with the help of D flip-flop and with some logic gates. The proposed work is mainly of double gate MOSFET (DG MOSFET) concept and transistor stacking method is used to reduce power dissipation and delay. This circuit is examined some parameter like power dissipation, delay and power delay product (PDP).Some Simulation like Tanner EDA tool and a 45 nm technology shows that the proposed JK flip-flop has lower power dissipation and small delay comparable to those of published an explicit-pulsed double-edge triggered JK flip-flop (EPDET-JKFF). In this circuit we observe the power dissipation decreases 21.87%. An improvement of 46.24% in PDP in JK flip-flop as compared to explicit-pulsed double edge triggered JK flip-flop.

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