Date of Publication :7th October 2016

Abstract: Multiplier is the most crucial part in any digital signal processing (DSP) system applications. Designing a reliable multiplier in the deep submicron era is a challenging task. Deep sub micron technology needs low power, high signal to noise ratio, reliability and etc. There exists always a trade of between low power and reliability. The approach in this paper is to compromise both the reliability and low power in designing a multiplier. This paper deals with, implementation of reliable low power multiplier for signed bits and performance analysis of sign extension and Baugh wooley multipliers in ANT (Algorithmic Noise Tolerant) architecture with fixed width RPR block.

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