Author : Mr.Kadgonda Annasaheb Kupade 1
Date of Publication :7th February 2017
Abstract: The focus of this Paper is to design Network Router and Verify the functionality of the nine port router for network on chip using Verilog qualifies the Design for Synthesis and implementation. This Design consists of Registers, FSM and FIFO’s. This Router design contains one input port and Eight output ports, and it has packet based Protocol. Router drives the incoming packet which comes from the input port to output ports based on the address contained in the packet. The router has an active low synchronous input ‘resetn’ which resets the router. Thus the idea is borrowed from large scale multiprocessors and wide area network domain and envisions on chip routers based network. This helps to understand how router is controlling the signals from source todestination based on the header address.
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