Author : Ankita Gupta 1
Date of Publication :19th April 2017
Abstract: We have proposed a 16-bit high-speed multiplier using VHDL. With this method, the number of partial products has been reduced and the carry during addition has been eliminated. It also reduces the switching power which makes this multiplier a low power multiplier as compared to other multipliers. Due to the elimination of carry, the delay has been reduced which makes it a faster multiplier as well. The RTL circuit is much simpler, this decreased circuit complexity which leads to a better circuit with lesser delay and easier, cost-efficient way to implement the hardware.
Reference :
-
[1] Douglas L. Perry “VHDL Programming by Example” Fourth Edi- tion,Tata McGraw-Hill Publications, DOI: 10.1036/0071409548. [2] J. Salivahanan, Arivazhagan S. Digital Circuits And Design, 3E. Vikas Publishing House Pvt Ltd, 2009.
[3] Volnei A. Pedroni, “Circuit Design with VHDL”, MIT Press, Cam- bridge, Massachussetts, 2004, ISBN 0- 262-16224-5 © 2004 Mass- achusetts Institute of Technology
[4]Fedra, Zbynek, and Jaromir Kolouch. "VHDL procedure for combinational divider." Telecommunications and Signal Process- ing (TSP), 2011 34th International Conference on. IEEE, 2011.
[5] Sadhu, A., & Bhattacharjee, P. (2014). Methodology of Standard Cell Library Design in. LIB Format. Journal of VLSI Design Tools & Technology, 4(1), 30-38.
[6] Pritam Bhattacharjee, Arindam Sadhu, Kunal Das. “A Register- Transfer-Level Description of Synthesizable Binary Multiplier and Binary Divider”, 2015.
[7] Kuan-Hung Chen, Yuan-Sun Chu, and Yu-Min Chen, Jiun-In Guo. “A High-Speed/Low-Power Multiplier Using an Advanced Spuri- ous Power Suppression Technique”, 2007, 1-4244-0921-7/07 on IEEE.
[8] Premananda B.S., Samarth S. Pai, Shashank B., Shashank S. Bhat. “Design and Implementation of 8-Bit Vedic Multiplier”, IJA- REEIE Vol. 2, Issue 12, December 2013.
[9] Ryosuke Nakamoto, Sakae Sakuraba, Takeshi Onomi, Shigeo Sato, and Koji Nakajima. “4-bit SFQ Multiplier Based on Booth Encoder”, IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 21, NO. 3, JUNE 2011.
[10] Juny Mary Jose, Reen Paul. “A High Speed Booth Wallace Multi- plier Using Pipelining Technique”, IJAREEIE Vol. 5, Special Issue 4, March 2016.
[11] Ashenden, Peter J. "VHDL standards." Design & Test of Comput- ers, IEEE 18.5 (2001): 122-123