Open Access Journal

ISSN : 2394 - 6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

ISSN : 2394-6849 (Online)

Design of AES-256 with Three Stage Pipelining S-Box Using Logic Gates

Author : Pujari Munaswamy 1 N.Dilipkumar 2 N.Pushpalatha 3

Date of Publication :17th March 2017

Abstract: The cipher is the component which is responsible for performing encryption or decryption on blocks of input data, while the key expander is responsible for preparing the input key for use by the cipher in each round. The Advance Encryption Standard (AES) is composed of four different functions that are repeated in a number of rounds. These are byte substitution, shift row, mix column, and add round key. The AES algorithm is capable of using cryptographic keys of 128, 192, and 256 bits to encrypt and decrypt data in blocks of 128 bits. The number of rounds in AES is variable and depends on the length of the key, i.e10 rounds for 128-bit key, 12 rounds for 192-bit key and 14 rounds for 256-bit key. Each of these rounds uses a different 128-bit round key, which is calculated from the original AES key. When a key of size 256 bits is used, the number of rounds are repeated is equal to 14. The function Sub Bytes is the only non-linear function in AES, operating on each of the state bytes independently. The 16 input bytes are substituted by looking up a fixed table (S-box) given in design. The result is in a matrix of four rows and four columns. It substitutes all bytes of the State using a look-up table called S-Box. A more suitable method of implementing the S-Box is to use composite field approach for calculating multiplicative inverse in a Galois Field GF(28) followed by an affine transformation in the binary extension field , which is based on combinational logic. An efficient design is three stages pipelining for the byte substitution phase. The proposed Three Stages Pipelining S-Box Using Logic gates and efficient in terms of delay and area.

Reference :

  1. [1] FIPS 197, “Advanced Encryption Standard (AES)”, November 26, 2001.

    [2] Marko Mali, Franc Novak and Anton Biasizzo “Hardware Implementation of AES Algorithm” – Journal of ELECTRICAL ENGINEERING, Vol. 56, No. 9-10, 2005, 265-269.

    [3] Behrouz A. Forouzan and Debdeep Mukhopadhyay “Cryptography and Network Security” (2nd edition).

    [4] L.Thulasimani,“A Single Chip Design and Implementation of AES-128/192/256 Encryption Algorithms”- International Journal of Engineering Science and Technology, Vol. 2(5), 2010, 1052-1059.

    [5] Nation Institute of Standards and Technology (NIST), Data Encryption Standard (DES), National Technical Information Service, Sprinfgield, VA 22161, Oct. 1999.

    [6] J. Daemen and V. Rijmen, “AES Proposal: Rijndael”, AES Algorithm Submission, September 3, 1999.

    [7] J. Nechvatal et. al., Report on the development of Advanced Encryption Standard, NIST publication, Oct 2, 2000.


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