Date of Publication :8th August 2024

Abstract:The underlying theme of the work is to obtain maximum performance with minimum leakage power consumption and no significant timing violations. This starts by loading an inefficient design having timing violations that exceeds 8000nS for setup and 45ns for hold in the post route stage, coupled with a staggering leakage power exceeding 200mW. Addressing these issues becomes the cornerstone of the initial phase, as several strategies are deployed to rectify the timing discrepancies, and optimize leakage power consumption, such that there exist no significant timing violations and the leakage power consumption stays below the 100mW mark. The next aim is to reduce the chip size, which shall take timing and leakage reduction db consecutively as input and perform a trade-off analysis between power and performance while reducing the chip area. The idea is to first optimize all three parameters individually and then analyze the compromises on the other two parameters, to obtain the best of all three worlds, where all three parameters can be optimized in a controlled fashion such that no parameter goes beyond a limit which might affect the design closure in later stages.

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