Date of Publication :March 2026

Abstract: The given paper includes the complete design and its implementation of an 8-bit, asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) in a 90 nm CMOS technology, using Cadence Virtuoso. The reason why SAR ADCs are favored within low-power, medium-resolution applications is their low power consumption as well as them being scalable to smart nodes of advanced CMOS technology. The suggested design uses bootstrapped sample and hold circuit, binary weighted capacitive digital to analog converter (CDAC), dynamic comparator and asynchronous SAR logic unit. The resulting Walden design fJ per conversion-step Figure-Of- Merit (FOM) places this design at a place that is appropriate to be used in calculating in-memory AI cores, medical sensors, and IoT implementations. The paper has carried out a detailed literature research on the current methods of designing a SAR ADC, has laid down the theoretical basis such as sampling theory and principles of charge-redistribution, and depicted a complete architecture of building an energy-efficient data converter in present day CMOS.

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