International Journal of Engineering Research in Electronics and Communication Engineering (IJERECE)

Monthly Journal for Electronics and Communication Engineering

Volume4,May 2017,

Topic : Design of Capacitor-less Low Drop-out Voltage Regulator for 100mA Load Current in 90nm Technology

Authors:Mr. Nagendra Kumar N || Mr. Kumar N Krishna Murthy

Abstract:A capacitor-free CMOS low-dropout regulator (LDO) for system-on-chip applications to reduce board space and external pins is presented. The 1.5 V LDO with a power supply of 1.8 V with settling time of 0.5 μs is implemented in GPDK 90nm CMOS technology for load currents up to 0 -100 mA with a drop-out voltage of 300 mV. Simulation results show that the LDO achieves a PSR of -43.741 dB up to 1 kHz and -39.130 dB up to 1MHz. The LDO achieves Line regulation of 6.38mV/V and Load Regulation of 0.027 mV/mA. The proposed LDO design has less output ripple, fast transient response, and achieves current efficiency of 83.33%. T he area acquired by the layout of the design is approximately equal to 0.0299μm2 .Thus, the presented capacitor-less LDO voltage regulator is suitable for SoC solutions.

Keywords: Capacitor-less, low drop-out regulator (LDO), power supply rejection (PSR), System on Chip (SoC).

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DOI: 01.1617/vol4/iss5/pid30918


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IMPACT FACTOR: 3.689

ISSN(Online): 2394-6849

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Thomson Reuters ID : q-6288-2016.
ORCiD Research ID : 0000-0001-9540-6799

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Journal Code : IJERECE
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