Open Access Journal
ISSN : 2394 - 6849 (Online)
International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)
Open Access Journal
International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)
ISSN : 2394-6849 (Online)
Reference :
[1] P. Reyes, P. Reviriego, J. A. Maestro, and O. Ruano, “New protection techniques against SEUs for moving average filters in a radiation environment,” IEEE Trans. Nucl. Sci., vol. 54, no. 4, pp. 957–964, Aug. 2007.
[2] M. Hatamian et al., “Design considerations for gigabit ethernet 1000 base-T twisted pair transceivers,” Proc. IEEE Custom Integr. Circuits Conf., pp. 335–342, 1998.
[3] H. Yamasaki and T. Shibata, “A real-time image-feature-extraction and vector-generation vlsi employing arrayed-shift-register architecture,” IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 2046–2053, Sep. 2007.
[4] H.-S. Kim, J.-H. Yang, S.-H. Park, S.-T. Ryu, and G.-H. Cho, “A 10-bit column-driver IC with parasitic-insensitive iterative charge-sharing based capacitor-string interpolation for mobile activematrix LCDs,” IEEE J. Solid-State Circuits, vol. 49, no. 3, pp. 766–782, Mar. 2014.
[5] S.-H. W. Chiang and S. Kleinfelder, “Scaling and design of a 16-megapixel CMOS image sensor for electron microscopy,” in Proc. IEEE Nucl. Sci. Symp. Conf. Record (NSS/MIC), 2009, pp. 1249– 1256.
[6] S. Heo, R. Krashinsky, and K. Asanovic, “Activity-sensitive flip-flop and latch selection for reduced energy,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 15, no. 9, pp. 1060–1064, Sep. 2007.
[7] S. Naffziger and G. Hammond, “The implementation of the nextgeneration 64 b itanium microprocessor,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2002, pp. 276– 504.
[8] H. Partovi et al., “Flow-through latch and edgetriggered flip-flop hybrid elements,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 138–139, Feb. 1996.
[9] E. Consoli, M. Alioto, G. Palumbo, and J. Rabaey, “Conditional push-pull pulsed latch with 726 fJops energy delay product in 65 nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2012, pp. 482–483
[10] V. Stojanovic and V. Oklobdzija, “Comparative analysis of masterslave latches and flipflops for high-performance and low-power systems,” IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 536– 548, Apr. 1999.
[11] J. Montanaro et al., “A 160-MHz, 32-b, 0.5- W CMOS RISC microprocessor,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1703–1714, Nov. 1996.
[12] S. Nomura et al., “A 9.7 mW AACdecoding, 620 mW H.264 720p 60fps decoding, 8- core media processor with embedded forwardbodybiasing and power-gating circuit in 65 nm CMOS technology,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2008, pp. 262–264
[13] Y. Ueda et al., “6.33 mW MPEG audio decoding on a multimedia processor,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2006, pp. 1636–1637.
[14] B.-S. Kong, S.-S. Kim, and Y.-H. Jun, “Conditional-capture flip-flop for statistical power reduction,” IEEE J. Solid-State Circuits, vol. 36, pp. 1263–1271, Aug. 2001.
[15] C. K. Teh, T. Fujita, H. Hara, and M. Hamada, “A 77% energy-saving 22-transistor singlephaseclocking D-flip-flop with adaptive-coupling configuration in 40 nm CMOS,” in IEEE Int. SolidState Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2011, pp. 338–339.