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[2]Peiyi Zhao, Student Member, IEEE, Tarek K. Darwish, Student Member, IEEE, and Magdy A. Bayoumi, Fellow, IEEE, “High-Performance and Low- Power Conditional Discharge Flip-Flop” IEEE Trans on VLSI Systems, MAY 2004

[3]K.G.Sharma, Tripti Sharma, B.P.Singh, Manisha Sharma, “Modified SET D-Flip Flop Design for LowPower VLSI Applications”, IEEE, 2011

[4]Yin- Tsung Hwang, Jin- Fa Lin, and Ming- Hwa Sheu, “Low-power pulsetriggered flip-flop design with conditional pulse-enhancement scheme”, IEEE Transactions on VLSI Systems, 2012.

[5]Kalarikkal Absel, Lijo Manuel, and R K Kavitha, Member, IEEE, “Low- Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic” IEEE Transactions on VLSI Systems, September-2013

[6]Marco Lanuzza, Ramiro Taco, “Improving Speed and Power Characteristics of Pulse-Triggered FlipFlops”. IEEE 2014

[7] Natsumi Kawai, Shinichi Takayama, “A Fully Static Topologically Compressed 21 Transistor Flip Flop with 75% Power saving”, IEEE journal on Solid State Electronics 2014

[8]Jin-Fa Lin, “Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme” IEEE Transactions on VLSI Systems, January- 2014

[9]Deepak Berwal, Ashish Kumar and Yogendera Kumar, “Low Power Conditional Pulse Control with Transmission Gate Flip-Flop” International Conference on Computing, Communication and Automation (ICCCA2015)

[10]Liang Geng, Jizhong Shen, Congyuan Xu – “Design of flip flops with clock gating and pull-up control scheme for power–constrained and speed– insensitive applications”-IET journals 2015

[11] Massimo Alioto- Elio Consoli Gaetano Palumbo, “Flip Flop Design in Nanometer CMOS”, Springer.

[12] L Wilson, “International technology roadmap for semiconductors (ITRS)” Semiconductor Industry Association, 2013

[13]More Moore “International technology roadmap for semiconductors (ITRS)”, 2015