International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Volume4,August 2017,

Topic : A comparative study of Excess Loop Delay Compensation Techniques in Continuous Time Delta- Sigma Modulators

Authors:Aditi Singh || Kumaravel S

Abstract:Continuous time ∑∆ Convertor is an highly power efficient modulator which has overcome the pipeline and Discrete time modulator as they require more number of high speed gain stages.Morever it is has an aliasing free Nquist band which is made available by oversampling and an on chip filter is also present.The input is resistive with no sampling so it is easier to drive the entire modulator with miniscule noise and an on- chip clock conditioner is used.There are several drawbacks associated with CTDSM like clock jitter and excess loop delay.In this paper different techniques to reduce Excess Loop Delay(ELD) in a continuous time delta sigma modulator is analysed and presented. .

Keywords: Delta-Sigma; Oversampling ;Clock jitter; Excess Loop Delay(ELD);Continuous Time ∑∆ Modulator (CTDSM).

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DOI: 01.1617/vol4/iss8/pid86409


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Dr.Zhongfu Tan
National Professor,
North China Electric Power University,
CHINA


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