International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Volume4,August 2017,

Topic : Design and Implementation of 12-T SRAM Cell in 32nm FinFET Technology

Authors:Kishore Kumar K || Radha B. L

Abstract:The primary downside of utilizing CMOS transistors is high power utilization and high leakage current. FinFET has turned into the most encouraging substitute for CMOS which has less short channel effects compared to CMOS technology. In low power applications, as the technology is scaling down leakage current and leakage power are the most noticeable problems for SRAM cell. The interest for static random access memory (SRAM) is expanding with extensive utilization of SRAM in System On- Chip and VLSI circuits. In order to design low power devices leakage current and power dissipation must be kept low. To reduce this dissipation conventional 12T SRAM is implemented using FinFET technology. In this paper power consumption during hold, read and write operations of CMOS 12T SRAM cell with FinFET based 12T SRAM cell are compared with the help of HSPICE simulator.

Keywords: FinFET, SRAM, HSPICE, BSIM-CMG Model, Power Dissipation

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DOI: 01.1617/vol4/iss8/pid83940


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Editor-in-Chief

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Dr.Zhongfu Tan
National Professor,
North China Electric Power University,
CHINA


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