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[7] V.Gupta and M.Anis, Member, IEEE "Statistical Design ofthe 6T SRAM bit Cell," IEEE Transactions On Circuits And Systems-I: Regular Papers, Vol. 57, No. 1 , January 2010 .

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[10] Ambrish Mall, Suryabhan Pratap Singh, Manish Mishra, Geetika Shrivastava, “Analysis Of 12t Sram Cell For Low Power Application” Deportment of Electronics, DDUGU Gorakhpur (273009),(U.P), INDIA. Amity School of engineering & Technology.

[11] K.G.Dharani,“Comparative Analysis of 6 Transistor, 8 Transistor and 12 Transistor SRAM Memories” Research Scholar,Karpagam University, Coimbatore Tamilnadu, India.