International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Volume4,October 2017,

Topic : FPGA Implementation of Address Bit Generation Block & Memory Interface Unit for Microcode Based Memory BIST Controller

Authors:Vadde SeethaRama Rao || Chilumula.RamBabu

Abstract:Memories are the most universal components today. Almost all system chips contain some type of embedded memory, such as ROM, SRAM, DRAM and flash memory. Testing of these memories is a challenging task as testing time, overhead area and cost of the test plays an important role during testing. The direct accessing of embedded memories is highly difficult. The testing of these memories done through a BIST (Built-in-self-test) Controller The Microcode based Memory BIST controller can be proven to be one of the best methods to test the memories. For this we are using March C/C+ algorithms, since March based tests are simple and possess good fault coverage. Microcode based Memory BIST consists of Program counter, Instruction decoder, Address generation block and Memory interface unit. This paper deals with the implementation of Address generation block, Memory interface unit for a Microcode based Memory BIST controller by using March C/C+ algorithms. Address generation block gives the address of the memory to the Memory interface unit and the Memory interface unit of MCMBIST controller acts as an interface between other blocks of MCMBST Controller and Memory under test. It has Address register, Data register, Control register, Multiplexers and Comparator. Address register takes the address from Address generation block, stores it for the fault diagnosis. Data register takes the data from Instruction decoder, processes and stores it. Control register takes read or write information from Instruction decoder and stores in it. The information from all these registers passed through the Multiplexers and to the memory under test for testing of all locations of memory. March C/C+ algorithms applied to Memory which under test. These blocks are designed by using Verilog HDL code, simulated by NC Verilog compiler and synthesized by RTL Compiler. These blocks are integrated with program counter and instruction decoder to form a Microcode based Memory BIST Controller.

Keywords: BIST, March C/C++, Micro Code, Verilog, HDL

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DOI: 01.1617/vol4/iss10/pid98031


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Editor-in-Chief

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Dr.Zhongfu Tan
National Professor,
North China Electric Power University,
CHINA


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ISSN(Online): 2394-6849

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