International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Volume4,November 2017,

Topic : Design of Convolution Using Vedic Multiplier

Authors:M.Anusha || P.Srinivasa Rao

Abstract:In this paper, a novel approach for implementing convolution of two finite length sequences using Vedic multiplier in Cadence tool is proposed. In this, Urdhva Triyagbhyam method is presented. The proposed implementation uses modified hierarchical design approach, which efficiently and accurately speeds up the computation without compromising with the area. The 4×4 bit multiplication modules are implemented using small 2×2 bit multiplier. The proposed design is Convolution Using Vedic multiplier has less power and low speed compared other multiplier existed earlier. The design of Convolution is compared different technologies i.e. 45nm,90nm, 180nm and results are compared. When comparing these three technologies, 45nm technology requires less power and delay. The design is implemented using cadence tool in using virtuoso schematic editor, virtuoso symbol editor, and ADEL simulator..

Keywords: Vedic multiplier,Conolution,Cadence tool.

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DOI: 01.1617/vol4/iss11/pid32154


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Dr.Zhongfu Tan
National Professor,
North China Electric Power University,
CHINA


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