International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Volume4,March 2017,

Topic : Design and Implementation of a High Speed Multiplier Using Reversible Logic

Authors:Vinutha P || Praveen Kumar Y G

Abstract:The core of all the digital signal processor(DSPs) are its multipliers and the speed of the DSPs is mainly determined by the speed of its multipliers. Latency and throughput are the two important parameters associated with multiplication algorithm performed in DSP application. The performance of multiplication in terms of speed and power is crucial for most of the digital signal processor applications. In this paper, a design of 32 bit multiplier using the nikilam sutra to minimize the power delay product of multipliers intended for high performance and low power applications..

Keywords: vedic multiplier, nikilam sutra architecture, reversible logic

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DOI: 01.1617/vol4iss3pid019


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Editor-in-Chief

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Dr.Zhongfu Tan
National Professor,
North China Electric Power University,
CHINA


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ISSN(Online): 2394-6849

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Thomson Reuters ID : q-6288-2016.
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Journal Code : IJERECE
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