Open Access Journal

ISSN : 2394 - 6849 (Online)

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

Open Access Journal

International Journal of Engineering Research in Electronics and Communication Engineering(IJERECE)

Monthly Journal for Electronics and Communication Engineering

ISSN : 2394-6849 (Online)

Reference :

  1. 1. M. Alioto and G. Palumbo, “Design Strategies for Source Coupled Logic,” IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications”, vol. 50, no. 5, pp. 640-653, May 2003.

    2. G. Diaz , L. Aranda and M. Hernaindez “A Comparison between Noise- Immunity Design Techniques for Dynamic Logic Gates’, IEEE International Symposium on Circuits and Systems,” vol. 1, pp. 484-488, 2006.

    3. L. Ding and P. Mazumder “On Circuit Techniques to Improve Noise Immunity of Dynamic Logic”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 9, pp. 910-924.

    4. HARRY J.M. VEENDRICK, “Short-Circuit Dissipation of Static CMOS Circuitry and Its Impact On the Design OF Buffer Circuits,” IEEE journal of solid state circuits, vol sc-19, no 4, August 1984.

    5. C. Kim, S. Ookjung , K. H. Baek and S. M. Kang (2002) “High Speed CMOS Circuits with Parallel Dynamic Logic and Speed-Enhanced Skewed Static Logic,” IEEE Transactions on circuits and systems II: Analog and digital signal processing, vol. 49, no. 6, pp. 434-439, May 2002.

    6. J.H. Lou and J.B. Kuo “A 1.5-V CMOS All-NLogic True-Single- Phase Bootstrapped DynamicLogic Circuit Suitable for Low Supply Voltage and High-Speed Pipelined System Operation,” IEEE Transactions on Circuits and Systems, vol. 46, no. 5, pp. 628-631.

    7. A. Rao, TH. Haniotakis, Y. Tsiatouhas and H. Djemil “The Use of Pre- Evaluation Phase in Dynamic CMOS Logic”, IEEE Computer Society Annual Symposium on VLSI New Frontiers in VLSI Design, pp. 270-271, 2005.

    8. Shamim Akhtar and Saurabh Chaturvedi, “A Novel method for Dual Output Dynamic Logic Using SCL Topology”, International Conference on signal Processing and Integrated Networks (SPIN), 2014.

    9. A. Tajalli and Y. Leblebici “Leakage Current Reduction using Sub-Threshold Source Coupled Logic”, IEEE Transactions on Circuits and Systems, vol. 56, no. 5, pp. 374-378, May 2009


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